This Getting Started Guide will explain how to get started with developing for the free and open RISC-V ISA, both in simulation and on physical implementations.

The Guide focuses on running standard operating systems - Zephyr and Linux - on popular RISC-V platforms with minimum effort.

It will be expanded with time to cover more platforms and scenarios.

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. It’s both academia- and industry friendly, open to scrutiny, built from scratch with security and modern use cases in mind. The standard is driven by a Foundation with more than 130 members, including Google, Western Digital, NVIDIA, NXP and many other industry leaders.

For details about the ISA and the Foundation, see the RISC-V website.


The source code for this Guide can be found on the RISC-V Foundation’s GitHub - while its compiled version is automatically generated using Read the Docs.

We encourage you to contribute - see the project’s README for details.